1. Field of the Invention
The present invention generally relates to floating point processors in high speed digital computers and, more particularly, to an improved method to compute an approximation of the reciprocal of a floating point number in the IEEE (Institute of Electrical and Electronics Engineers) format.
2. Background Description
Floating point arithmetic units are commonly used in central processing units (CPUs) of digital computers, especially high performance superscalar processors such as reduced instruction set computers (RISC). An example of a RISC processor is the IBM PowerPC® used in the IBM RISC System/6000 computer. Such processors typically include an input/output (I/O) unit interfacing with an instruction/data cache and a branch processor, one or more fixed point processors and one or more floating point processors.
The semantics of floating point instructions has not been as clear cut as the semantics of the rest of the instruction set. To address this problem, the computer industry has standardized on the floating point format by IEEE standard 754-1985. The IEEE standard defines 32-bit and 64-bit floating point formats. Each consists of (from left to right) a sign bit, an e-bit exponent and an f-bit fraction. The exponent is assumed to be biased with bias 2(e−1)−1 and it is assumed that an implicit 1 is to be appended to the front (left) of the fraction. The IEEE 32-bit format has e=8 and f=23. The IEEE 64-bit format has ee=11 and f=52. The present invention will work for these and similar formats (with different values for e and f). The IEEE standard also defines the result of arithmetic operations on floating point numbers in these formats.
Of the four basic arithmetic operations of addition, subtraction, multiplication, and division, division is the most difficult to implement efficiently. One way of performing a floating point division x/y is to compute it as x×(1./y). This can be done by finding a relatively low accuracy initial approximation to 1./y, using an iterative method to refine the low accuracy approximation to the desired accuracy, and then multiplying by x. This method is particularly attractive when it is unnecessary to obtain the exact IEEE specified value for x/y. However, the method requires a method for finding an initial approximation to the reciprocal of the floating point number y. The present invention provides such a method.
The problem of finding a good easily computed initial approximation to the reciprocal of a floating point number is well known and has been solved in various ways in both hardware and software. The IBM PowerPC® architecture defines a FRES operation which has generally been implemented using a simple lookup table. A table size of 2k will produce an approximation with k+1 good bits. More complicated hardware methods are also known. An initial approximation with 4.3 good bits can be computed with a single integer subtraction. This method has been used in IBM's vector MASS software.
U.S. Pat. No. 5,563,818 to Agarwal et al., U.S. Pat. No. 6,163,791 to Schmookler et al., and U.S. Pat. No. 6,240,433 to Schmookler et al. include methods for finding an initial approximation to the reciprocal of a floating point number that are similar to the present invention in that they combine table lookup with a floating point multiply-add to produce the initial approximation. However, the Agarwal et al. and Schmookler et al. methods are relatively complex in their implementations. What is needed is a simpler method which simplifies both hardware and software implementations and results in a quicker computation of an estimate of the reciprocal of a floating point number in IEEE format.